Blog Post

I²C is one of the most widely used serial communication buses in embedded systems powering sensors, memory devices, microcontroller interfaces, and more. Yet one feature often misunderstood, even by experienced engineers, is clock stretching. For more embedded engineering insights, visit Jenex Technovation.

Clock stretching is essential for ensuring reliable communication between fast masters and slower slaves. This guide breaks down the electrical principles, timing, implementation behavior, and real-world challenges every engineer should know. You can also explore our advanced firmware solutions on the Embedded Firmware Solutions page.

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Why Clock Stretching Exists

I²C is a synchronous serial protocol where:

• The master generates SCL (clock)
• The slave responds on SDA

But what if the slave is busy?

• A sensor is finishing an ADC conversion
• An EEPROM is completing a write cycle
• A microcontroller-based slave is processing an interrupt
• The slave needs extra time to load a byte
• The slave has a slower internal oscillator

Clock stretching lets the slave say: “Wait, I’m not ready yet.”

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Electrical Principle Behind Clock Stretching

I²C uses open-drain outputs:

• Devices can pull the line LOW
• A pull-up resistor brings the line HIGH
• No device actively drives SCL HIGH

So if the master releases SCL but the slave keeps it LOW, the bus stays LOW.

This electrical behavior enables clock stretching. For deeper electrical-level details, the official NXP I²C specification is helpful: NXP I²C-Bus Specification.

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How Clock Stretching Works (Step-by-Step)

Normal SCL cycle:

• Master pulls SCL low
• Master releases SCL → pull-up brings it high
• Master starts the next clock pulse

When the slave stretches:

• Master releases SCL
• Slave keeps SCL low
• Master must wait
• Slave releases SCL

Slaves may stretch during:

• Address ACK
• Byte transfers
• ACK/NACK generation
• Repeated START

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Timing Diagram (Simplified)

Master Intent:    __    __        __    __
SCL (master):  __|  |__|  |__  __|  |__|  |__
Actual SCL:    __       ________       _______
SCL (bus):   _|  |_____|        |_____|       |_

                     ^ Slave holds SCL low

Key point: The master must check the physical SCL bus level, not its internal state.

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Why Slaves Stretch the Clock

Common reasons include:

• Internal processing delays (ADC, filtering)
• EEPROM write-time delays
• Data preparation time
• MCU interrupt or slow firmware

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I²C Specification Rules

Important rules derived from the spec and TI application notes such as TI AN-SLVA704:

• Allowed after any SCL low period
• No maximum stretch time defined
• Master must wait until SCL goes HIGH
• Supported in Standard, Fast, Fm+
• Not supported during High-Speed mode data phase

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Real-World Issues and Pitfalls

1. Masters that poorly support stretching

• ESP8266 hardware I²C
• Some ARM Cortex-M controllers
• Faulty silicon versions

Result: Data corruption.

2. Long stretches causing timeouts

• Watchdog resets
• Transfer timeout
• Bus lockup

3. Stretching during START/STOP edges

Poor drivers may misinterpret edges → bus errors.

4. Multi-master challenges

Stretching interacts with arbitration & synchronization.

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How Microcontroller Hardware Handles Stretching

Master Side

A reliable master continuously samples SCL:

while (SCL_is_low()) {
    wait();
}

Slave Side

MCUs stretch SCL when buffers aren’t ready:

drive_SCL_low();
prepare_data();
release_SCL();

This is handled automatically in many MCUs (STM32, PIC, AVR, ESP32).

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Can Clock Stretching Be Disabled?

• Slaves: Some sensors allow enabling/disabling
• Masters: Typically always support it, but with timeout control

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Stretching vs Setup/Hold Timing

Clock stretching does NOT alter:

• Data setup time
• Data hold time
• Valid data window

It only pauses communication.

A Simple Analogy

Master: “Send the next bit!”
Slave: “Hold on… okay, continue.”

Clock stretching acts like a “pause button” on the bus.

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Summary

Clock stretching is a fundamental I²C feature that ensures slow slaves can safely keep up with fast masters. Understanding its electrical behavior, timing, and implementation is key to building robust I²C communication systems. For expert embedded engineering support, explore our Embedded Firmware Solutions.

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Written by Jenex Tech Embedded Engineering Team